(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to protect a via hole opening, in a low dielectric constant (low k), layer, from a subsequent photoresist development procedure.
(2) Description of Prior Art
The objective of the semiconductor industry to continually improve the performance of semiconductor chips, has led to the use of copper metal interconnect structures, as well as to the use of low dielectric constant (low k), layers, such as fluorinated silica glass (FSG), or hydrogen silsesquioxane, (HSQ), featuring dielectric constants of about 2.9, for these low k, interlevel dielectric (ILD), layers. The performance enhancement is realized via reduction of RC delay constant for the semiconductor chip, via use of lower resistivity copper, when compared to counterparts fabricated with more resistive aluminum or tungsten, as well as lower capacitance resulting from the use of low k layers, when compared to counterparts employing higher dielectric layers such as silicon oxide. However the definition of dual damascene type openings, formed in low k layers, used to accommodate metal structures, can however encounter specific contamination problems during the opening of the dual damascene shape. One such contamination problem encounter during a dual damascene opening, in low k layers, is a via poisoning phenomena. After formation of the narrow diameter, via hole component of the dual damascene opening, in the low k layer, using a first photoresist shape and a dry etching procedure, the first photoresist shape is removed and a second photoresist shape, featuring a wide diameter opening, is formed to supply the masking needed to allow another dry etching procedure to create the trench shape component of the dual damascene opening, in a top portion of the low k layer. However during the development cycle of the second photoresist shape, unwanted release of amine, or hydroxyl type elements components, evolving from the low k layer exposed in the via hole shape, can poison the narrow diameter opening by formation of unwanted products, such as organic type mushroom shapes. The unwanted mushroom type shapes, now located in the via hole shape, adversely influence the ability to form a metal, or copper structure, in that via hole component of the dual damascene opening.
An option available for preventing evolution of amine or hydroxyl type species, from the low k layer during development of the dual damascene, trench shape, is the use of a silicon oxide layer deposited on the surfaces of the low k layer, exposed in the narrow diameter, or via hole component, of the dual damascene opening. The minimum thickness of the silicon oxide liner needed to prevent via hole poisoning, has been found to be about 500 Angstroms. Therefore to obtain a conformal, 500 Angstrom, silicon oxide liner, a deposition mode such as a conformal, low pressure chemical vapour deposition (LPCVD), procedure, is needed. However the elevated temperatures used for the LPCVD procedure would result in degradation to existing metal structures. Other deposition procedures, such as a plasma enhanced chemical vapour deposition (PECVD), procedure, although employing lower deposition temperatures, do not offer the conformality, or step coverage, needed to adequately protect the low k layer, exposed in the via hole shape.
The present invention will therefore describe a novel procedure for forming a silicon oxide liner layer, for a dual damascene application, via use of a liquid phase deposition (LPD), mode. The LPD deposition of the silicon oxide liner on the surfaces of the low k layer, exposed in the via hole component of the dual damascene opening, in accomplished with excellent conformality, and performed at a temperature in which degradation of existing metal structures is avoided. Prior art, such as Lin et al, in U.S. Pat. No. 5,612,239, describe an LPD procedure used to selectively form a silicon oxide layer on exposed silicon surfaces, for subsequent insulator spacer formation. That prior art however does not describe the novel application of this present invention, featuring the use of the LPD silicon oxide liner at a specific stage of formation of a dual damascene opening in a low k layer.
It is an object of this invention to form a copper interconnect structure and a copper via structure in a dual damascene opening, located in a low k layer.
It is another object of this invention to coat the surfaces of the low k layer, exposed in the via hole component, of the dual damascene opening, with.a silicon oxide layer, prior to the photolithographic procedure used to define the trench opening component of the dual damascene opening.
It is still another object of this invention to use a liquid phase deposition (LPD), procedure to form the silicon oxide layer on the surfaces of the low k layer, exposed in the via hole opening component of the dual damascene opening.
In accordance with the present invention a method of forming a dual damascene opening in a low k layer, featuring a silicon oxide layer used to coat the surfaces of the via hole component of the dual damascene opening, prior to the formation of the trench opening component shape of the same dual damascene opening, is described. A composite low k layer, comprised of an underlying low k layer, a thin silicon nitride stop layer, and an overlying low k layer, is formed on an underlying, lower level, metal interconnect structure. A first photoresist shape is used as an etch mask to allow a first dry etch procedure to define a narrow diameter, via hole opening, in the composite low k layer, exposing a portion of the top surface of the lower level, metal interconnect structure. After removal of the first photoresist shape a conformal, silicon oxide layer is formed, via a low temperature, liquid phase deposition (LPD), procedure, on portions of the composite low k layer, exposed in the via hole opening, as well as formation of the silicon oxide layer on the lower level, metal interconnect structure exposed at the bottom of the via hole opening. A second photoresist shape is then used as an etch mask to allow a second dry etch procedure to define a wide diameter, trench shape opening in the overlying low k layer, with the selective second dry etch procedure terminating at the appearance of the thin silicon nitride stop layer. The second dry etch procedure also exposes a portion of the top surface of the lower level, metal interconnect structure, via selective removal of the portion of LPD silicon oxide located on the bottom of the via hole opening. The resulting dual damascene opening, comprised of a wide diameter, trench opening component, in the overlying low k layer, and comprised of a narrow diameter, via hole opening component, featuring LPD silicon oxide spacers, located in the thin silicon nitride stop layer, and in the underlying low k layer, is the used to accommodate a dual damascene type, copper structure.